L1 Instruction Cache TLB

The Ember core includes an L1I cache which is virtually-indexed and physically-tagged (VIPT). This means that the physical address associated with the requested cacheline must be resolved in order to determine whether or not it is present in any of the L1I cache ways.

The L1I translation lookaside buffer (TLB) is a small cache for page table entries which is accessed in parallel with the L1I cache’s tag and data arrays. When the L1I TLB is able to provide a physical page number, L1I tag matching and way selection can proceed without any additional latency. Otherwise, TLB misses must invoke the hardware page table walker (PTW) and cause the L1I cache access to incur substantial latency.

class ember.front.itlb.L1ICacheTLBReadPort(param: L1ICacheParams)

L1I TLB read port.

class Request(param: L1ICacheParams)

A request to L1I TLB to resolve the physical page number for the provided virtual page number.

class Response(param: L1ICacheParams)

A response from the L1I TLB containing a physical page number.

class ember.front.itlb.L1ICacheTLBFillRequest(param: L1ICacheParams)

A request to write an entry into the L1I TLB.

class ember.front.itlb.L1ICacheTLB(*args, src_loc_at=0, **kwargs)

L1 instruction cache TLB (translation lookaside buffer).

This is a small fully-associative cache for page table entries. Each entry in the TLB associates a virtual page number (VPN) to a page table entry (PTE).

Replacement Policy

Currently, the replacement policy is random. The index for each fill request is generated by an LFSR.

At some point, this will probably be replaced with the tree-based pseudo least-recently used (PLRU) policy.

Ports: